18luck新利电竞 集成电路学院研究员，博士毕业于复旦大学微电子学院，拥有10年以上模拟射频芯片设计经验，迄今使用28nm, 65nm, 130nm和180nm CMOS工艺共流片10次以上。研究方向为射频和模拟信号集成电路设计，其中主要包括高能效抗干扰无线收发机芯片设计，无线数据与能量协同传输接收机芯片设计，时域信号处理/频率生成芯片设计（PLL/ILCM/TDC/DTC）和全无线脑机接口芯片设计。迄今共发表22篇国际会议论文与期刊论文（一作或通讯作者15篇）。其中以第一作者或通讯作者身份在集成电路设计领域顶级会议ISSCC和集成电路设计领域顶级期刊JSSC上共发表论文7篇。在2019和2020年的国际电路与系统年会（ISCAS）上发表的论文分别被评为“生物医疗方向最佳论文”（Best paper award at ISCAS2019 BioCAS track ）和“最佳学生论文”（Best student paper award at ISCAS2020）。同时担任JSSC,TCAS-I,TCAS-II,TMTT等集成电路设计领域高水平期刊的审稿人。获授权发明专利16项。

研究方向：

• 低功耗抗干扰无线接收机芯片设计（ISSCC x2, JSSC x2, TMTT x1, ASSCC x1, RFIC x1，ISCAS x1）；

• 无线能量与数据协同传输芯片设计(ISSCC x1, JSSC x1)；

• 脑机交互/电生理信号提取芯片设计(CICC x1, TBCAS x1, TCAS-II x1, ISCAS x2)；

• 时域信号处理/频率生成芯片设计(ISSCC x1, RFIC x1, TCAS-I x1, ISCAS x2)；

主要论著：(ISSCC x 4, JSSC x 3，^*：通讯作者)

• D. Ye^*, R. van der Zee, B. Nauta, "A 915 MHz, 175 μW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance" Special Issue of IEEE Journal of Solid State Circuits (JSSC) on ISSCC 2016. (Invited Paper)

• D. Ye^*, R. van der Zee, B. Nauta, “An Ultra-Low-Power Receiver Using Transmitted-Reference and Shifted Limiters for In-Band Interference Resilience.” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016. (Highlighted Paper in ISSCC 2016)

• D. Ye^*, R. Xu and C. -J. Richard Shi, “A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019

• D. Ye^*, Y. Wang, Y. Xiang, L. Lyu, H. Min and C. –J. R. Shi., “A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation,” IEEE Journal of Solid-State Circuits (JSSC), May 2020.

• D. Ye^*, R. Xu, C. –J. Richard Shi, “A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain,” IEEE Journal of Solid-State Circuits (JSSC), Nov. 2021.

• Y. Wang, D. Ye^*, L. Lyu, H. Min, C. -J. Richard Shi, “A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

• R. Xu, D. Ye^*, and C. -J. Richard Shi, “A 0.021mm² 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.

• D. Ye^*, Y. Tu, W. Gong, and C. –J. Richard Shi, “A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB Rejection to CW/AM Interference,” IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2021.

• D. Ye^*, R. Xu, L. Lyu, C. –J. Richard Shi. “A 2.46GHz, −88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.

• D. Ye^*, P. Lu, P. Andreani, R. van der Zee, " A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid-ΔΣ-DAC and Charge Re-timing," International Symposium on Circuits and Systems (ISCAS), May 2013.

• R. Xu, D. Ye^*, and C. –J. Richard Shi, “Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors,” IEEE Transaction on Circuits and Systems I (TCAS-I), Mar. 2023. (TCAS-I Highlight Paper in July 2022)

• H. Ren, D. Ye^*, B. Chen, X. Jin, W. Gong, R. Xu, and C. –J. Richard Shi, “A 915MHz 19μW Blocker-Enhanced Wake-Up Receiver with Frequency-Hopping Two-Tone Modulation Achieving 53dB Tolerance to In-Band Interference,” IEEE RFIC Symposium (RFIC), Jun. 2023.

• L. Lyu, D. Ye^*, R. Xu, G. Mu, H. Zhao, Y. Xiang, Y. Tu, Y. Zhang and C.- J. R. Shi, “A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110dB AFE PSRR and Supporting 54Mb/s Symbol Rate, Meter-Range      Wireless Data Transmission,” IEEE Transaction on Circuits and Systems II (TCAS-II), May 2020.

• G. Mu, D. Ye^*, L. Lyu^*, X. Zhao and C. –J. R. Shi, “An 8-Channel Analog Front-End with a PVT-Insensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021.

• R. Xu, D. Ye^*, L. Lyu, and C. –J. R. Shi, “A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction,” IEEE RFIC Symposium (RFIC), Jun. 2020.

• L. Lyu, D. Ye, and C. –J. R. Shi, “A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65nm CMOS,” Transactions on Biomedical Circuits and Systems (TBCAS), May 2020.

• H. Ren, D. Ye, et al. "A 19-μW Block-Tolerant Wake-Up Receiver With -90-dBm Energy-Enhanced Sensitivity," Transactions on Microwave Theory and Techniques (TMTT), May 2023.

• L. Lyu, D. Ye, C.-J. Richard Shi. “A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2019. (Received the best paper award @ ISCAS2019 BioCAS track)

• Y. Tu, R. Xu, D. Ye, L. Lyu and C. –J. R. Shi, “A 400 MHz, 8-bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification,” IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020.